1. Technical Field
The embodiments herein relate to a semiconductor integrated circuit, and more particularly to a receiver circuit that can be used in a semiconductor integrated circuit to increase operational speed and integration.
2. Related Art
The increasing processing speed of modern computers has increasingly required low-power, high-speed semiconductor integrated circuits. Due to this trend, in recent years, a multi level or a multi bit technology that achieves high storage density has been used as an information transmission technology between a semiconductor integrated circuit and a broader system. Multi level technology represents data using a plurality of signal levels and bits, instead of represented binary information using two levels, i.e., high and low.
For example, unlike conventional memory circuits in which unit cell that stores only high-level or low-level information, a unit cell in a multi level memory circuit can store data using four voltages or more.
However, conventional multi-level technology requires large amounts of power and can produce errors due to signal distortion during a high-speed operation.
A conventional receiver circuit acts as the interface circuit between the broader system and the particular integrated circuit. The receiver circuit is responsible for receiving signals to be input to the integrated circuit, buffering them, and then forwarding them to internal portions of the circuit. The receiver should transmit the signals to the internal circuits without generating additional signal distortion. Therefore, equalization is often used to ensure adequate signal margin and/or to compensate for signal attenuation losses.
In relation to the above, related technologies have been disclosed in “A Reconfigurable Fully-Integrated 0.18-gm CMOS Feed Forward Equalizer IC for 10-Gb/sec Back Plane Links” (ISCAS 2006), in which a Feed-Forward Equalization (FFE) architecture is described, and “8-Gb/s Source-Synchronous I/O Link With Adaptive Receiver Equalization, Offset Cancellation, and Clock De-Skew” (IEEE JSSC Vo. 40), in which a Decision Feedback Equalization (DFE) is described. However, such implementations are complicated and require a large circuit area. Additionally, FFE implementations tend to amplify signal noise in addition to the data information, which can be problematic.